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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3.6.3
3.6.4
3.6.5
3.6.6
EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]
After reset, by default, the CPU performs 16-bit accesses to the EMIF and USB registers and data space.
To perform 8-bit accesses to the EMIF data space, the user must set the BYTEMODE bits to 01b for the
"high byte" or 10b for the "low byte" in the EMIF System Control Register (ESCR). Similarly, the
BYTEMODE bits in the USB System Control Register (USBSCR) must also be configured for byte access.
Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
After hardware reset, the DSP executes the on-chip bootloader from ROM. As the bootloader executes, it
selectively enables the clock of the peripheral being queried for a valid boot. If a valid boot source is not
found, the bootloader disables the clock to that peripheral and moves on to the next peripheral in the boot
order. After the boot process is complete, all of the peripheral clocks will be off and all domains in the ICR,
except for the CPU domain, will be idled (this includes the MPORT and HWA). The user must enable the
clocks to the peripherals and CPU ports that are going to be used. The peripheral clock gating control
registers (PCGCR1 and PCGCR2) are used to enable and disable the peripheral clocks.
Pullup/Pulldown Inhibit Registers (PDINHIBR1/2/3) [1C17h, 1C18h, and 1C19h,
respectively]
Each internal pullup and pulldown (IPU/IPD) resistor on the device DSP, except for the IPD on TRST, can
be individually controlled through the IPU/IPD registers (PDINHIBR1 [1C17h] , PDINHIBR2 [1C18h], and
PDINHIBR3 [1C19h]). To minimize power consumption, internal pullup or pulldown resistors should be
disabled in the presence of an external pullup or pulldown resistor or external driver. Section 3.8.1 ,
Pullup/Pulldown Resistors , describes other situations in which an pullup and pulldown resistors are
required.
When CV DD is powered down, pullup and pulldown resistors will be forced disabled and an internal bus-
holder will be enabled. For more detailed information, see Section 5.3.2 , Digital I/O Behavior When Core
Power (CV DD ) is Down .
Output Slew Rate Control Register (OSRCR) [1C16h]
To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF
and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the
device I/O pins, namely CLKOUT and EMIF pins, to either fast or slow slew rate. The slew rate feature is
implemented by staging/delaying turn-on times of the parallel p-channel drive transistors and parallel n-
channel drive transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but
ultimately the same number of parallel transistors are used to drive the output high or low. Thus, the drive
strength is ultimately the same. The slower slew rate control can be used for power savings and has the
greatest effect at lower DV DDIO and DV DDEMIF voltages.
60
Device Configuration
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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